The present disclosure relates to non-volatile storage.
Semiconductor memory has become increasingly popular for use in various electronic devices. For example, non-volatile semiconductor memory is used in cellular telephones, digital cameras, personal digital assistants, mobile computing devices, non-mobile computing devices and other devices. Electrically Erasable Programmable Read Only Memory (EEPROM) and flash memory are among the most popular non-volatile semiconductor memories. With flash memory, also a type of EEPROM, the contents of the whole memory array, or of a portion of the memory, can be erased in one step, in contrast to the traditional, full-featured EEPROM.
Both the traditional EEPROM and the flash memory utilize a floating gate that is positioned above and insulated from a channel region in a semiconductor substrate. The floating gate is positioned between the drain and source diffusion regions. A control gate is provided over and insulated from the floating gate. The threshold voltage (VTH) of the transistor thus formed is controlled by the amount of charge that is retained on the floating gate. That is, the minimum amount of voltage that must be applied to the control gate before the transistor is turned on to permit conduction between its drain and source is controlled by the level of charge on the floating gate.
Groups of memory cells may be associated with a bit line. In one approach, memory cells are arranged as NAND strings, with each NAND string being associated with one bit line. A selected memory cell in the group may be sensed by applying a voltage to the selected memory cell and sensing a signal on the bit line. During programming, different voltages can be applied to the bit line to control the rate at which the selected memory cell programs.
Typically, a program voltage VPGM applied to the control gate during a program operation is applied as a series of pulses that increase in magnitude as programming progresses. In one possible approach, the magnitude of the pulses is increased with each successive pulse by a predetermined step size, e.g., 0.2-0.4 V. VPGM can be applied to the control gates of flash memory cells. In the periods between the program pulses, verify operations are carried out. That is, the programming level of each element of a group of cells being programmed in parallel is read between successive programming pulses to determine whether it is equal to or greater than a verify level to which the element is being programmed.
After a given memory cell on the word line selected for programming reaches its intended threshold voltage, programming may be inhibited for that memory cell. In one approach, programming is inhibited by applying an inhibit voltage to bit lines associated with NAND strings without a memory cell presently being programmed. In one approach, programming is allowed by grounding bit lines associated with NAND strings having a memory cell presently being programmed. In one approach, some memory cells undergo slow programming by applying an intermediate voltage to bit lines associated with their NAND strings.
Charging up the bit lines associated with inhibited NAND strings can result in a very large current. It is possible for the current to be so large that it causes the voltage of a power supply to drop. Therefore, performance of the memory device may be impaired.
One possible solution is to limit the rate at which the bit lines are charged, and then use a monitoring circuit that detects the speed at which the bit lines are charging up. The program pulse can be applied when the bit lines are fully charged. In effect, the time between starting to charge the bit lines and applying the program pulse is dynamically adjusted. When the bit lines present a heavy load and charging is slow, the program pulse needs to be applied later. However, when the bit lines present a lighter load and charging is faster, the program pulse may be applied sooner. Therefore, programming speed is increased. However, this approach requires special circuitry, which incurs a chip size penalty. Also, this circuitry must be tested to ensure that it works properly, which adds to the cost of developing the memory device.